Hi,
I am now working on the delay locked loop simulation. I use a circuit level design for the voltage-controlled delay line, and verilog-a model for the phase detector and charge pump. My target is to simulate the in-band pnase noise (jitter) coming from the delay line will be suppressed compared with open-loop case(not including any noise from phase detector and charge pump). However, this is only observed while I choose the noise type to source, but not the same effect if I choose jitter as the noise type and plot the jee spectrum. Is there any one having the experience on these kind of simulation? I saw that jitter simulation is recommended especially for measuring the jitter for square wave. On the other hand, there are many documents talking about integrate the phase noise to get the jitter. Should the jitter caculation result from different noise type (source or jitter) be consistent to each other?
This is the link to my simulation result plot:
https://docs.google.com/a/berkeley.edu/file/d/0B6zK04zfHkAEZmM3MzJtVkw5MW8/edit?usp=sharing
Thanks,
ycyeh