hai,
i am designing VCO in cadence-virtuoso ADE L(180nm) topology is attached below where i have to know how to plot graph C Vs Voltage. Capacitance is parallel combination of two PMOS varactors (PM2 and PM3) and also when i simulated the ckt with 1.2V i am getting low peak to peak voltage swing how to increase the output voltage peak to peak swing
can any one help me in this regard
thanks in advance![]()
i am designing VCO in cadence-virtuoso ADE L(180nm) topology is attached below where i have to know how to plot graph C Vs Voltage. Capacitance is parallel combination of two PMOS varactors (PM2 and PM3) and also when i simulated the ckt with 1.2V i am getting low peak to peak voltage swing how to increase the output voltage peak to peak swing
can any one help me in this regard
thanks in advance