Quantcast
Channel: Cadence RF Design Forum
Viewing all articles
Browse latest Browse all 956

problem with nodeset and ic Ringoscillator design

$
0
0

Hello, 

I am simulating ring oscillator to match current and frequency values from simulation run by some other ppl. Those guys used SPF spice file and I have extracted DSPF file. After running simulation I am getting slight deviation in values, in order to tackle it , I need to see the response of active devices so I comment out all parasitic capacitors and set very low resistance to parasitic resistors that it will behave as a short. The simualtion run time was 50ns and before modifying R's and C's it was taking 24 min on average, but Now in 2 days it just passed through 3ns . When I did i set the nodeset values to certain nodes, but these nodes are not added in netlist and virtuoso gives me this error :

Ensure that the specified schematic names are valid.

/I0/I3/I0/net8 /I0/I3/I0/net31

These nodes are on the first level going down to the hierarchy (descend ). If I select any node from top level then its added to the netlist. After this I creted spectre .ic file and add these nodes there with their values, and then added this file as initial condition, even then the simulation is very very slow.

Any solution or suggestion that can help me to analyse the results only from the extracted transistors in my DSPF file.

Thanks


Viewing all articles
Browse latest Browse all 956

Trending Articles