Hi,
I am trying to design CMOS PA at mm-wave frequency by Cadence. I already set up the simulation to draw Pout contours by Load pull method. Now, my question is that if Cadence has this ability to draw PAE (Power Added Efficiency) contours or not? I already know the other software programs like ADS has such a capability of drawing PAE contour.
Moreover, as you know, the input impedance and therefore the input power does not remain constant as a result of load variation. Could you please help me figure out how to set up my simulation for the transistor to be driven by the maximum input power as long as the load impedance varies? Obviously, if this situation is not resolved, the output power contours is not valid.
Thanks.