Hello, I have an issue that my data falling edge is very close to the clock rising edge, thus logic '1' doesnt get sampled as you can see in the arrows in the last photo
so i got to the conclution that altough we have VDD at the gate there has to pass some minimal time for the mosfet to create an invertion layet(channel)
is there a way to simulate and see this amount of time in cadence virtuoso?
Thanks
