Dear all,
I am running a pss of a simple VCO verilog-A model, but there is an error found and pss is failed:
Warning from spectre.
WARNING (SPECTRE-16707): Only tran supports psfxl format, result of other analyses will be in psfbin format.
Error found by spectre during periodic steady state analysis `pss'.
ERROR (SPCRTRF-15177): HB analysis doesn't support behavioral module components with hidden states found in component 'vco_8G_pss'. Skipped.
Error message from ahdl:
/home/SSS/vco_8G_pss/veriloga/veriloga.va, at line 33: idtmod not support in hb analysis.
/home/SSS/vco_8G_pss/veriloga/veriloga.va, at line 34: idtmod not support in hb analysis.
Rewrite the module and rerun.
Analysis `pss' was terminated prematurely due to an error.
modelParameter: writing model parameter values to rawfile.
And here is the code I used in VCO verilog-A model:
`include "discipline.h"
`include "constants.h"
`include "constants.vams"
`include "disciplines.vams"
(* instrument_module *)
module vco_8G_pss(vin, voutP, voutN);
input vin; voltage vin; // input terminal
output voutP, voutN; voltage voutP, voutN; // output terminal
parameter real vmin=0; // input voltage that corresponds to minimum output frequency
parameter real vmax=2 from (vmin:inf); // input voltage that corresponds to maximum output frequency
parameter real vc=1/2*(vmax+vmin) from (vmin:inf); // maximum output frequency
parameter real fmin=7.372e9 from (0:inf); // minimum output frequency
parameter real fmax=8.628e9 from (fmin:inf); // maximum output frequency
parameter real fc=1/2*(fmax+fmin) from (fmin:inf); // maximum output frequency
parameter real va=1; // amplitude
parameter real kvco=100M;
real freq, phaseP, phaseN;
integer n;
analog begin
// compute the freq from the input voltage
// freq = (V(vin)-vc)*(fmax - fmin) / (vmax - vmin) + fc;
freq = kvco*(V(vin)-vc) + fc;
// bound the frequency (this is optional)
if (freq > fmax) freq = fmax;
if (freq < fmin) freq = fmin;
// phase is the integral of the freq modulo 2 pi
phaseP = 2*`M_PI*idtmod(freq, 0.0, 1.0, -0.5);
phaseN = `M_PI+2*`M_PI*idtmod(freq, 0.0, 1.0, -0.5);
V(voutP) <+ va*(1+sin(phaseP));
V(voutN) <+ va*(1+sin(phaseN));
// bound the time step to assure no cycles are skipped
$bound_step(0.2/freq);
end
endmodule
Is there any approach to run pss in VCO verilog-A model?
Looking forward any responses.
Thanks all.