Hi ,
How do I simulate IRR of complex filter. ? ( A transient simulation of an IQ mixer followed by a complex filter and then look at dft of the output waveforms is one way )
Is there a cadence documentation for the same ?
Thanks,
Regards,
Vishal
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Complex filter : Image Reject Ratio (IRR) calculation
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cadence pz analysis
for a two stage opa as Allen described,with a compensation cap,with the cadence pz analysis,found that there are 5 poles,5 zeros ,is that right? somebody said that should cancel some pole-zero pair,how should I do that?
Is the pz analysis correct? How others usually do?
that I have another question,I found that nmos's Kp is 6 times of pmos' in tsmc 0.18um technology when I design a rail to rail constant-gm opa ,but in books ,it is usually 2-3 times.Is it because of in sub-micron process ,some complicated effect?
Thanks!
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Transient results as starting point in PSS
Hello,
Could we use the transient analysis results as a stabilization point (tstab) for PSS analysis? If so, how could we acheive it? Is there any documentation on this? Any inputs will be helpful.
Prakash.
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Confusion regarding captab output ( Drain & Gate ; Gate & Drain)
Dear All,
I was trying to find out the Cgd value of a MOS.
I did cpatab dc analysis.
But I am confused as it is showing two differnent values for Drain-&-Gate capacitance & for Gate-&-Drain capacitance.
The more confusing is :- It is showing difference in the Fixed value capacitance. How physically it is possible ?
What is the Cgd value indeed ?
Could anybodyplease tell & clarify regarding this.
I have attached the cap-Table.
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K Stability factor
Hi
I use SP analysis in ADE L and draw the KF (stability factor).
The result is different compared to the K factor derived from any known equations (I got the equations from Pozar's book). i.e. I use for example, the Yij parameters and use my own equations for K.
How I can get more information about how KF in SP analysis is calculated in ADE L ?
Thanks,
Hamid
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analogLib in cadence 6.1.5 (LNA simulation)
Hello,
I was looking for some help. I am a graduate student who is looking to perform some s parameter analysis on a LNA. The version of cadence licensed to my university (UMKC) is 6.1.5. Most tutorials have the schematic drawn with parts from the library called analogLib. My university seems to only have the NCSU CDK tools and libraries. Is it possible to do s parameter analysis using these libraries? or is there some way to add analogLib to my university's license?
I had this sort of analysis in mind.
https://www.youtube.com/watch?v=uKyoJ3jZbWI
Thanks
Marouf Khan
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custom inductor/tline layout Assura LVS issue
Hi there,
I need to incorporate a few custom designed transmission lines and inductors in to a TSMC 65nm tapeout. I found a document from another TSMC pdk about using Assura ?blackboxcell option to do LVS and RCX. The basic procedure is that you copy n2port element into the PDK lib and name it as a new cell (for example n2port_d1). Then copy symbol view to auLvs and auCdl views, do some editing in CDF. Next, create layout view for this cell with pins matching n2port _d1(which are t1, b1, t2, b2). In the higher level tapeout, when doing LVS, list n2port_d1 cell in the ?blackboxcell option. My problem is that Assura goes into n2port_d1 cell and decide the pins (t1, b1, t2, b2) are floating and discarded all of them. Then Assura discovered these pins are missing in layout, and terminated the LVS.
Here is how my runName.erc file looks like
***** Begin Label Report *****
Label in cell 'nmos_rf layout tsmcN65 macro="nmos_rf"':
info: Assign pin label "S" at (2.520, 1.000) to layer `metal4'.
info: Assign pin label "G" at (2.520, 2.180) to layer `metal3'.
info: Assign pin label "D" at (2.520, -0.530) to layer `metal2'.
info: Assign pin label "B" at (5.855, 1.000) to layer `metal1'.
Label in cell 'n2port_d1 layout tsmcN65':
info: Floating label discarded: "t1" at (1.200, 0.500).
info: Floating label discarded: "t2" at (153.300, -1.200).
info: Floating label discarded: "b2" at (153.300, -8.400).
info: Floating label discarded: "b1" at (0.700, -8.500).
info: Floating label discarded: "t2" at (153.400, -1.200).
info: Floating label discarded: "t1" at (1.200, 0.500).
info: Floating label discarded: "b2" at (153.400, -8.300).
info: Floating label discarded: "b1" at (0.800, -8.400).
Label in cell 'TL_test1_core layout tsmc65debug':
info: Assign pin label "P1" at (56.100, -208.950) to layer `metal3'.
info: Assign pin label "P2" at (54.550, -38.600) to layer `metal3'.
info: Assign pin label "gnd!" at (49.600, -205.800) to layer `metal2'.
info: Assign pin label "vdd!" at (54.350, -43.400) to layer `metal2'.
***** End of Label Report *****
My problem seems similar to the one discussed in this thread, but I didn't find a final answer
http://www.cadence.com/Community/forums/p/14022/22986.aspx#22986
I'd appreciate your input. Also, could you please point me to relevant reference documents where I could learn more about how to do custom cell LVS and extraction with Assura and Calibre?
thanks,
Ran
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Seeking for Help in PSS Analysis
Hi i am a beginner in using Cadence. I am designing a LNA and i meet problem when come to PSS analysis. My pss analysis could not run and terminated. I am clueless and have no idea. Could anyone please help? Here i attached my schematic and the simulation log pictures.![]()
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Seeking for Help in PSS Analysis
Hi i am a beginner in using Cadence. I am designing a LNA and i meet problem when come to PSS analysis. My pss analysis could not run and terminated. I am clueless and have no idea. Could anyone please help? Here i attached my schematic and the simulation log pictures.![]()
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Measuring Load-Pull contours - Spectre User Guide example
Hi,
I am trying to generate load-pull contours to determine the optimal load of my amplifier. I work with virtuoso 6.1.5. I follow the instructions given in "Virtuoso Spectre Circuit Simulator RF Analysis User Guide", which is based on the rfExample library. I modify my schematic (check&save w/ success), the configure Spectre as expected.
But when I start the parametric analysis, new variables appear in the "Design Variables" list : thetaOff, iPata and i59. I right-click to find them on the schematic but it doesn't work (variable 'thetaoff' not found on the schematic).
If I choose a default value for these variables, then I get the following errors (they appear several times) :
Error found by spectre in `portAdapter', during circuit read-in.
ERROR (SFE-874): "input.scs" 54: Unexpected comma ",". Expected close parenthesis.
ERROR (SFE-683): "input.scs" 54: Badly formed parameters statement.
ERROR (SFE-874): "input.scs" 54: Unexpected operator "*". Expected end of file or end of line.
Warning from spectre in `portAdapter', during circuit read-in.
WARNING (SFE-702): "input.scs" 55: Use of the comma character in node lists is not supported.
Error found by spectre in `portAdapter', during circuit read-in.
ERROR (SFE-874): "input.scs" 55: Unexpected operator "*". Expected end of file or end of line.
ERROR (SFE-874): "input.scs" 55: Unexpected operator "*". Expected end of file or end of line.
ERROR (SFE-874): "input.scs" 55: Unexpected operator "*". Expected end of file or end of line.
ERROR (SFE-678): "input.scs" 55: Statement is not in Spectre format. Use `simulator lang=spice' to introduce spice language sections.
Error found by spectre during circuit read-in.
ERROR (SFE-874): "input.scs" 72: Unexpected quoted string ""theta". Expected close parenthesis or comma.
I don't really understand where it comes from (the portAdapter component ? the file input.scs ?) ; nor how to solve it.
In my lab, no one already encountered this problem or know where it could come from.
Thanks,
Fabien![]()
I am trying to generate load-pull contours to determine the optimal load of my amplifier. I work with virtuoso 6.1.5. I follow the instructions given in "Virtuoso Spectre Circuit Simulator RF Analysis User Guide", which is based on the rfExample library. I modify my schematic (check&save w/ success), the configure Spectre as expected.
But when I start the parametric analysis, new variables appear in the "Design Variables" list : thetaOff, iPata and i59. I right-click to find them on the schematic but it doesn't work (variable 'thetaoff' not found on the schematic).
If I choose a default value for these variables, then I get the following errors (they appear several times) :
Error found by spectre in `portAdapter', during circuit read-in.
ERROR (SFE-874): "input.scs" 54: Unexpected comma ",". Expected close parenthesis.
ERROR (SFE-683): "input.scs" 54: Badly formed parameters statement.
ERROR (SFE-874): "input.scs" 54: Unexpected operator "*". Expected end of file or end of line.
Warning from spectre in `portAdapter', during circuit read-in.
WARNING (SFE-702): "input.scs" 55: Use of the comma character in node lists is not supported.
Error found by spectre in `portAdapter', during circuit read-in.
ERROR (SFE-874): "input.scs" 55: Unexpected operator "*". Expected end of file or end of line.
ERROR (SFE-874): "input.scs" 55: Unexpected operator "*". Expected end of file or end of line.
ERROR (SFE-874): "input.scs" 55: Unexpected operator "*". Expected end of file or end of line.
ERROR (SFE-678): "input.scs" 55: Statement is not in Spectre format. Use `simulator lang=spice' to introduce spice language sections.
Error found by spectre during circuit read-in.
ERROR (SFE-874): "input.scs" 72: Unexpected quoted string ""theta". Expected close parenthesis or comma.
I don't really understand where it comes from (the portAdapter component ? the file input.scs ?) ; nor how to solve it.
In my lab, no one already encountered this problem or know where it could come from.
Thanks,
Fabien
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Can a beginner ask here for some help?
Hi,
I am a student at local faculty of Electrical Engineeing, and I just recently started using Cadence Virtuoso. The thing is, I am also employed, and I'm attending this course in RF electronics at the department which I don't belong to.
We had a couple of lab exercises till now, using Virtuoso, and that's about it.
Soon, I will have to start with the project which is requred in this course, and the goal of the project is to design one of the following: LNA, mixer, oscillator, PLL or power amplifier. And we also have to choose if it's going to be for the receiver or for the transmitter. I think I didn't miss anything...
I am still a liitle behind in theory, so I am learning from Razavi's book at home when I find the time (my job is very time-consuming). Also, most of the other students have divided between themselves to work in pairs and triples; since I don't know anybody, I'll work my part solo. I am also not managing to get any hep from the professor; he is a good guy, but very busy unfortunately.
I was wondering if someone here would be kind to me give a few pointers, 'cause I desperately need them:
1) Which of these projects would be the easiest to implement? I usually don't go for the path of least resistance, but in this case... the fact is that I'm a total beginner and I have to do this solo.
2) Is there any help or demo project, or something, that could show me the ropes. not to start from scratch, so to speak? I assume there is, but I don't have the luxury of starting Cadence and browsing through it; I can only use it at the lab across the city, when I find the time after work.
3) Other than Razavi's book, is there any other piece of literature you would recommend for the beginner? The book is great, but sometimes I do have a liitle trouble with some parts of the book.
Any help is greatly appreciated and thanks for your time!
Marko
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error in creating netlist
I followed the tutorial in the link below about creating netlist file for hspice simulation.
http://www.ece.rice.edu/~cavallar/cadence/tutorial/netlist.html
I got two problems. Hope you could help.
1. I don't see "extracted" view at all as from step 3 in the link.
2. However, I omitted that step and open "schematic" view and followed all remained steps.
Finally, I ran ac simulation. However, I got the error below.
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Impedance measurement
Sir/Madam,
I have been designing a Differential drive rectiifer for UHF passive RFID in 130nm CMOS process. As the design of rectifier completes I got stuck with the impedance measurement, i.e. for finding input impedance of rectifier using Cadence Virtuoso. As it is a non-linear circuit which simulation should I choose to find or how should I find the input impedance of rectifier in Cadence Virtuoso, which is essential for matching network design.
Thanks and Regards,
jithin
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ERROR (SPECTRE-4080): There are no components in the circuit.
Dear Friends,
I use Cadence Virtuoso version 6.1.5 with Spectre MMSIM 071.
I tried to simulate a simple circuit by it. But I have faced this problem:
Loading /opt/spectre/MMSIM071/tools.lnx86/cmi/lib/5.0/libinfineon_sh.so ...
Loading /opt/spectre/MMSIM071/tools.lnx86/cmi/lib/5.0/libphilips_sh.so ...
Loading /opt/spectre/MMSIM071/tools.lnx86/cmi/lib/5.0/libsparam_sh.so ...
Loading /opt/spectre/MMSIM071/tools.lnx86/cmi/lib/5.0/libstmodels_sh.so ...
/usr/lib/gcc/i586-suse-linux/4.4/cc1: /opt/spectre/MMSIM071/tools/lib/libstdc++.so.6: version `GLIBCXX_3.4.11' not found (required by /usr/lib/libppl_c.so.2)
/usr/lib/gcc/i586-suse-linux/4.4/cc1: /opt/spectre/MMSIM071/tools/lib/libstdc++.so.6: version `GLIBCXX_3.4.9' not found (required by /usr/lib/libppl_c.so.2)
/usr/lib/gcc/i586-suse-linux/4.4/cc1: /opt/spectre/MMSIM071/tools/lib/libstdc++.so.6: version `GLIBCXX_3.4.11' not found (required by /usr/lib/libppl.so.7)
/usr/lib/gcc/i586-suse-linux/4.4/cc1: /opt/spectre/MMSIM071/tools/lib/libstdc++.so.6: version `GLIBCXX_3.4.9' not found (required by /usr/lib/libppl.so.7)
/usr/lib/gcc/i586-suse-linux/4.4/cc1: /opt/spectre/MMSIM071/tools/lib/libstdc++.so.6: version `GLIBCXX_3.4.11' not found (required by /usr/lib/libgmpxx.so.4)
Error found by spectre during initial setup.
ERROR (SPECTRE-4080): There are no components in the circuit.
Do you know how to solve it?
Thanks in advance
Shaa
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How to avoid Hidden State in VerilogA model for SpectreRF
Dear All,
I am a beginner in verilogA .
I wrote a code but when I ran PSS it showed hidden state in the code and didn't run.
My behavioural model is as below:-
// VerilogA for VERILOG_A_MODEL, HARD_LIMIT_GM, veriloga
`include "constants.vams"
`include "disciplines.vams"
module HARD_LIMIT_GM(in,out);
inout in,out;
parameter real vtrans = 0;
parameter real tdelay = 0 from [0:inf);
parameter real trise = 1p from (0:inf);
parameter real tfall = 1p from (0:inf);
parameter real Gm=-5m;
electrical in,out;
real vout_val;
analog begin
@ (cross(V(in) - vtrans, 1)) vout_val = 1;
@ (cross(V(in) - vtrans, -1)) vout_val = 0;
I(out) <+ Gm * transition( vout_val, tdelay, trise, tfall);
end
endmodule
Could anybody please tell how I can avoid the hidden state (vout_val ) ?
Kind Regards,
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ERROR (VACOMP-1008): Cannot compile ahdlcmi module library
Dear Friends,
I have faced to this problem, when I have added a VARICAP to my VCO circuit.
Error found by spectre during AHDL read-in.
ERROR (VACOMP-1008): Cannot compile ahdlcmi module library. Check the log file input.ahdlSimDB//bsource.va.bsource_1.ahdlcmi/Linux/../ahdlcmi.out for details. If the compiler ran out of memory, use 'setenv CDS_CMI_COMPLEVEL 0', and try again. If the reason for the failure was a syntax error, contact your Cadence Customer Support representative with the netlist, log files, behavioral model files, and any other information that can help identify the problem.
ERROR (SFE-91): Error when elaborating the instance bsource_1. Simulation should be terminated.
Does anybody know a solution for it?
Thanks in advance
Shaa
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Z parameters - Mason's invariant varies!
Hi
Adding the inductor at Source, the Z11 would become Z11+jwL and hence real(Z11) should remain unchanged. However, using SP analysis (Virtuoso - ADE L), by changing the inductor at Source, real(Z11) changes which results in variation of U (Mason's invariant which is supposed not to change with lossless reciprocal embedding).
I would appreciate if some one can help me understand why real(Z11) changes when I change the inductor in Source.
Thanks,
HKH
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Plot two variables vs. each other
Dear friends
In ADE-L, is it possible to sweep on variable "x" (e.g. frequency) and calculate y and z, and plot y vs. z ?
What I can do right now is to plot both y and z versus x and I do not know how to plot y vs. z.
Thanks a lot
HKH
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injection locked oscillator phase noise simulation using pss+pnoise
Hi all,
I am designing an injection locked vco. My simulation scenario for the phase noise is as follows:
1. Run the vco without the injection signal for 2 microseconds ; let it setttle to the free running frequency;
2. Start the injection signal and observe the phase noise...
Well, I need a periodic vsine source to generate the injection signal in the schematic; and this is the very source of an error in my pss simulation:
" 'V0' is a periodic input signal, which is inconsistent with autonomous circuits. "
this is what happens if I set cadence for phase noise simulation using the instructions given in the cadence Spectre manual.
I know... the instructions are for a 'normal' vco; but I was hoping that it would work for my injection locking case as well.
Question, as obvious it is by now :), how do we simulate the injection locked oscillator phase noise ?
Is there a way to conceal the periodic voltage source in the circuit so as not to piss the pss off ?
thanks,
calp.
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nonlinear resistance definition in Spectre
Hi, I need to model a nonlinear resistance in spectre but i don't know how to, pleas help me.
thanks alot.
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