Hello, I am trying to simulate a physical phenomena of charge injection from gate to source, as shown in the schematics bellow.
the principal says that when we switch voltage from VDD to 0 on the gate, although the charging has to stop there is still the curent flow from gate to sourse from the overlap parasitic capacitance.
I=C*dv/dt when voltage changes there is a current flow threw the capacitor.However when i tried to simulate this effect in cadence, i got a very idial behavior.
I trying to change the Width of the NMOS ,rise time fall time, it presents me an idial behavior.
Is there something i can do to see this effect in cadence virtuoso?
Thanks
FYI This is yefj , i had problem with my user and i was told by the cadence support to re-register :-) i will change my nick as soon as possible.
