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ELIC HDI
*Email: Walker.wang@fastturnpcbs.com*Skype: Walker（fastturnpcb）*Website:www.fastturnpcbs.com
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multiple Y-param results for varactor
Hello , i have built a varactor based on the theory shown bellow, on one hand i need to sweep control voltage on the other hand i need to have Y-param for every value of control, and convert it into...
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measuring node transient current
Hello, when i tried doing direct plot and wanted to measure the node current sighed in blue arrow.but it says that i should choose a terminal( i tried to put a port in between and hoose it) but still...
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simulating node capacitance charging
Hello , i am trying to build an RF frequency D FlipFlop as shown bellow.On the node Q signed by blue arrow i get a very abnormal charge and discharge behavior.On the first TG opening Q charges half the...
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ideal op amp comparator settings
Hello , i am using ahdlib library component called: OPAMP i want to convert its in a simple comparator for A/D .i want it to see who is bigger and output one of the supply voltages i put:gain:...
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Y param expression for calculator
Hello , i would like to verify an idial inductor using its Y-param.i have built a two port system as shown bellow and performed SP simulation for it.From the direct plot window there are only option...
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Phase Noise Analysis on a Gated Ring Oscillator
I am designing a Gated Ring Oscillator (GRO), To be used in a Time to Digital Converter (TDC). To get an idea about the performance of the GRO, I would like to perform a phase noise analysis.I already...
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How to use pss-pnoise output noise spectrum in pll excess phase model
HelloI ran PSS+Pnoise on LC VCO. Now i have output noise profile in sqr(v)/Hz vs offset frequency. Now i want to use this spectrum in PLL excess phase model(created in virtuoso) to check how PLL will...
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problem creating symbol of netlist subcircuit
Hello ,i am trying to import a spice subcircuit as symbol in schematics. Hspice text cellview was created where i entered my MOS subcircuit checked the syntax. (txt file of the model attached)After...
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cadence gpdk45 off grid problem
Hello, i am trying to implement an iverter design with Cadence gpdk45.my snipping grid is defined 0.005, as shown bellow.When i ran assura DRC with the rul file of gpdk45.It says there is off grip...
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Exporting Impedance data from Harmonic Balance after Loadpull analysis
Hi,I am running load-pull analysis on a circuit for a range of frequencies. I need to use this data in other tools such as matlab. I wondering how to export this data in terms of impedances and plot...
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pole zero analysis validation using ac sweep
Hello ,i have built a circuit and ran a POLE ZERO simulation on it, after that i took those poles and zeros and made a transfer function in MATLAB as shown bellow.After that i compared the MATLAB...
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captab simulation problem
Hello ,i am trying to imagine the flow of charge in this 1Ghz Flipflop shown bellow ,i have ran both DC and transient captab simulation as shown bellow.how ever it says that is an syntaxt error but...
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extraction parameters not recognised in hirarchy simulation
Hello,i have tried to simulate the extraction model of the layout inverter,i have build a hirarchy and defined the inverter to be the av_extracted file as shown bellow.However the transient simulation...
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PMOS netlist model Virtuoso syntax
Hello , i have a netlist model for LTSPICE which i want to implement for building an oscilator using spice text i have trying to import the model shown bellow.however when i do the check and save on...
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Beff parameter and saturation current
Hello i have created 25uA current threw the nmos and pmos at gpdk45nm technology for the purpose of creating an opamp.For NMOS in gate drain connection(saturation): W=120n L=1.2u After simulating i...
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ENVLP Anaylsis Questions
I've few question regarding ENVLP analysis and wireless simulations within it.1) Where can I find the actual values of important parameters after the analysis is finished..It seems that part of them...
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high frequency D flip flop for phase detector
Hello, i have succeeded to implement a phase detector using modification of xor logic circuit. how ever the more popular implementation is using D FLIP FLOP shown bellow.I have read many articles...
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icc.rules in cadence 6.1.7
Hi,I am using virtuoso 617 to do the auto-route by chip assembly router. However, there are some drc errors. I found out online that designer can import icc.rules file to define minimum width and...
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gpdk45 Gate source switch charge injection
Hello, I am trying to simulate a physical phenomena of charge injection from gate to source, as shown in the schematics bellow.the principal says that when we switch voltage from VDD to 0 on the gate,...
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