Dear All,
I wrote a code in Verilog A to generate four different clocks clk1, clk2, clk3 and clk4 from clk, as shown below. These clocks are used for switching in the filter. While doing PSS/PAC analysis for plotting the magnitude response of filter, its giving an error shown below, Could anybody please tell how can I avoid this. I am a beginner in Verilog A, the code is also posted for the reference.
Regards,
Jayaram
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ERROR In Running PSS/PAC...
Error found by spectre during periodic steady state analysis `pss'.
ERROR (SPCRTRF-15177): PSS analysis doesn't support behavioral module components with hidden states found in component 'JYR_CLKgen_VerA'. Skipped.
/home/jayaram/SCL_JYR_filter/JYR_CLKgen_VerA/veriloga/veriloga.va, declared in line 18: Hidden state variable: count
/home/jayaram/SCL_JYR_filter/JYR_CLKgen_VerA/veriloga/veriloga.va, declared in line 19: Hidden state variable: vout1
/home/jayaram/SCL_JYR_filter/JYR_CLKgen_VerA/veriloga/veriloga.va, declared in line 19: Hidden state variable: vout2
/home/jayaram/SCL_JYR_filter/JYR_CLKgen_VerA/veriloga/veriloga.va, declared in line 19: Hidden state variable: vout3
/home/jayaram/SCL_JYR_filter/JYR_CLKgen_VerA/veriloga/veriloga.va, declared in line 19: Hidden state variable: vout4
Analysis `pss' was terminated prematurely due to an error.
CODE:
`include "constants.h"
`include "disciplines.h"
module JYR_CLKgen_VerA(vclk, vclk1, vclk2, vclk3, vclk4);
input vclk;
output vclk1, vclk2, vclk3, vclk4;
electrical vclk, vclk1, vclk2, vclk3, vclk4;
parameter real vtrans_clk=0.9;
parameter real voh=1.8;
parameter real vol=0.0;
parameter real tdel = 0 from [0:inf);
parameter real trise = 0.1n from [0:inf);
parameter real tfall = 0.1n from [0:inf);
integer count;
real vout1, vout2, vout3, vout4;
analog begin
@(initial_step) begin
count = 0;
end
@ (cross(V(vclk) - vtrans_clk, 1.0)) begin
if (count == 0) begin
vout1 = voh;
vout2 = vol;
vout3 = vol;
vout4 = vol;
end
else if (count <= 7) begin
vout1 =vol;
vout2 = voh;
vout3 = vol;
vout4 = vol;
end
else if (count <= 20) begin
vout1 = vol;
vout2 = vol;
vout3 = voh;
vout4 = vol;
end
else if (count <= 31) begin
vout1 = vol;
vout2 = vol;
vout3 = vol;
vout4 = voh;
end
if (count<=31)
count = count+1;
else count = 0;
end
V(vclk1) <+ transition(vout1,tdel,trise,tfall);
V(vclk2) <+ transition(vout2,tdel,trise,tfall);
V(vclk3) <+ transition(vout3,tdel,trise,tfall);
V(vclk4) <+ transition(vout4,tdel,trise,tfall);
end
endmodule
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