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validating plot phase margin with STB simulation

Hello, I have built a closed loop amplifier  and  tested the gain and phase from the output to the minus input AC=1v source.I got about 70 degrees phase at 0dB amplitude,as shown in the plot bellow.

Afterward i placed an idial current source in the feedback loop, and set STB simulation as shown bellow ,pointing the current source as probe instance.

When i ran the simulation it gives me an error shown bellow  that phase marging could not been calculated.

Where did i go wrong setting STB simulation?
Thanks.

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