single path idial current not floowing threw transistor
Hello i Have ,defined 50uA idial current source which is suppose to flow straight to diode connected mosfet bellow.The other side of the current source connected to VDD.As you cant see bellow , all the...
View ArticleCan i use variables in custom eye mask coordinates?
Hi,We are generating custom eye mask for different voltages and data rates. we want to make the eye diagram co ordinates generic. so we used variables in the coordinates. I am using the 6.1.7 version....
View Articletransconductance frequency response problem
Hello , I am trying to make a Vout/Iin frequency response for the current mirror shown bellow.In the DC region the current mirror workes great.In order to make AC reponce for Iin/Vout i have added 1 to...
View ArticlePLL simulation error
Hello, I'm doing a transistor level PLL simulation for the first time and i'm getting this error:and this is the PLL circuit: from similar posts and answers here I got that one reason might be is...
View Articlematching op capacitanances with impedance plot
Hello , I am trying to validate my output impedance plot with the OP parameters of the mosfets connected to the output.the Cds and Cgd capacitances were shown in the zoomed plot bellow.i have made an...
View Articlevalidating plot phase margin with STB simulation
Hello, I have built a closed loop amplifier and tested the gain and phase from the output to the minus input AC=1v source.I got about 70 degrees phase at 0dB amplitude,as shown in the plot...
View ArticleSTB analysis of differential feedback amplifier
Hello, I ran succsefully STB analysis of a single ended amplifier by connecting Iprobe on the feedback loop shown bellow.Afterwards i have built a differential amplifier which has common mode...
View Articlegm/id with modern cadence virtuoso
Hello, I am trying to create an expression which is a combination of regular currect with OP gm. f(gm/id,vgs)All the manuals which i found are envolving a file system manipulation for creating such...
View ArticleLoop gain block for keeping DC
Hello , I was told that there is a block in Cadence Virtuoso wich keep the same DC value which is used for braking the loop and calculate loop gain.In the past inductance and capacitors where used for...
View Articleopen loop closed loop link via STB loop gain
Hello, I have built and amplifier which acts exactly like in the open loop behavior where the gain reduces as the bandwidth increases by the LOOP GAIN factor.(As shown bellow)However when i calculated...
View ArticleIncorrect flicker noise model in some devices
An error in the flicker noise model of some devices has been found that leads to incorrect results in pnoise, hbnoise and transient noise analysis. Details can be found at...
View ArticleWhether BSIM-IMG model suitable for passive mixer's IIP3 measurement in Spectre
Dear All,Just want to know whether BSIM-IMG model suitable for passive mixer's IIP3 measurement in Spectre ?Kind Regards,
View ArticlePowering a circuit with a rectifier
Hello,(schematic ADE L)I am currently trying to power an LNA with a rectifier (AC-DC). the rectifier takes 10us to charge and settle. The problem is when running transient, after 10us the LNA does show...
View ArticleFinding Gate Resistance of MOSFET in spectre-ADE.
Dear All,We are able to find the Cgg,Cgs, Cgd and other junction capacitance of the MOS in ADE.Is there any way we can find the Gate Resistance of MOSFET in spectre-ADE ?Kind Regards,
View Articleruler measurment which sums all sections passed at once
Hello, i am trying to calculate the total perimeter of the inductor.by pressing K i managed only to see the length of separate sections .Is there a way to see the total perimeter of the whole shape...
View Articlecomlex plot for gm_id method
Hello i am trying to create a plot of gm/Id(Id/W) of the nmos shown bellow.i know how to plot gm or Id separatly (as shown in the setting bellow)but how do i define the Y axes to be gm/Id and X axes...
View ArticleHow the "region" operating Point is determined by Spectre ADE
Dear All,For typical long channel, the condition for the saturation (active) region of NMOS is VDS > ( VGS-VTh).For short channel we can use vdssat for determining the active region of NMOS i.e....
View Articleproblem displaying OS param in calculator
Hello, i need to use OS param for building a formula, however it gives me an error shown bellow.When i try t plot gm or id the regular ADEL way or using OP, then it works fine but for some reasin the...
View ArticleHarmonic Index of PSS data is not found?
Hi,I am simulating a 32.768 kHz Pierce oscillator for phase noise. I have attached the details of my PSS+PNOISE setups in screenshots. Post completion of the analysis, I am unable to get the Direct...
View Articlecommon mode feedbak STB analysis question
Hello, i want to verify a certain point.I have a common mode feedback amplifier,which is not a regular feedback(from input to output)So STB could not work in this case because the feedback loop is not...
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