*Email: Walker.wang@fastturnpcbs.com
*Skype: Walker（fastturnpcb）
*Website:www.fastturnpcbs.com
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ELIC HDI
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multiple Y-param results for varactor
Hello , i have built a varactor based on the theory shown bellow, on one hand i need to sweep control voltage on the other hand i need to have Y-param for every value of control, and convert it into capacitance,so we have here multiple SP simulations for each value of CONTROL voltage, is that the correct order of simulating for creating the Capacitance vs Control plot,as shown bellow?
i know that we can use Goldengate to convert Y-param into capacitances (for certain frequency)
Thanks
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measuring node transient current
Hello, when i tried doing direct plot and wanted to measure the node current sighed in blue arrow.
but it says that i should choose a terminal( i tried to put a port in between and hoose it) but still its not working.
where did i go wrong?
Thanks
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simulating node capacitance charging
Hello , i am trying to build an RF frequency D FlipFlop as shown bellow.
On the node Q signed by blue arrow i get a very abnormal charge and discharge behavior.
On the first TG opening Q charges half the way. When TG closes, it charge Q till the end although its not suppose to charge at all at this step(closed TG) ,as shown in the last plot bellow.
Is there a way to see how much capacitance we have on node Q when TG opens?
Thanks.
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ideal op amp comparator settings
Hello , i am using ahdlib library component called: OPAMP i want to convert its in a simple comparator for A/D .
i want it to see who is bigger and output one of the supply voltages i put:
gain: 1.5M
freq_unitygain 8M
rin: 4M
vin_offset:30u
ibias:15n
slew rate:8M
rout: 70
positive supply 1.2 negative supply 0 vref =0.
i put two opposite sources switching from 0 to 0.6 at 1nsec period and instead of showing me in the output the replica of source1
it gives me a straight line at 0.8 V
where did i go wrong transforming it to comaprator?
Thanks
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Y param expression for calculator
Hello , i would like to verify an idial inductor using its Y-param.i have built a two port system as shown bellow and performed SP simulation for it.
From the direct plot window there are only option to view the Imaginary or the Real part of the Yparam where as in my formula i need the whole Complex number(as shown bellow).
When i imported the imaginary part it showed me imag(ypm('sp 1 1)).
I assumed ypm('sp 1 1) is Y11. so by this logic my formula need to be expressed as
(ypm('sp 1 1)+ypm('sp 2 2)+2*ypm('sp 2 1))/(ypm('sp 1 1)*ypm('sp 2 2)-ypm('sp 1 2)*ypm('sp 1 2)).
Afterwards i pressesed the button of "evaluate the buffer and express the result in a table" i got the table shown in the end.
The table has only real values, no complex numbers in it .
Where did i go wrong?
Thanks
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Phase Noise Analysis on a Gated Ring Oscillator
I am designing a Gated Ring Oscillator (GRO), To be used in a Time to Digital Converter (TDC).
To get an idea about the performance of the GRO, I would like to perform a phase noise analysis.
I already did some phase noise measurements using PSS and PNOISE from a regular ring oscillator, this work fine.
The challenge with the GRO is that the free running ring oscillator (1.127 GHz) is only enabled for a small period in time, this at a frequency of a the input reference clock (50MHz)
Running the PSS simulation on this circuit always ends up not able to converge. Is there someone that already performed phase noise measurements on a GRO?
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How to use pss-pnoise output noise spectrum in pll excess phase model
Hello
I ran PSS+Pnoise on LC VCO. Now i have output noise profile in sqr(v)/Hz vs offset frequency. Now i want to use this spectrum in PLL excess phase model(created in virtuoso) to check how PLL will filter this noise.
Please can you help me how to do this. Because i am not getting any source in virtuoso which can read spectrum csv file.
With Regards
Munish
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problem creating symbol of netlist subcircuit
Hello ,i am trying to import a spice subcircuit as symbol in schematics. Hspice text cellview was created where i entered my MOS subcircuit checked the syntax. (txt file of the model attached)
After that i am trying to create a simbol by create->celview From cellview. created a symbol as done a test bench as shown bellow.
However i get an error massage as shown in the attached log.Where did i go wrong importing my sub circuit as a symbol into schematics?
Thanks
community.cadence.com/.../spice.txt
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community.cadence.com/.../1300.log.txt
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cadence gpdk45 off grid problem
Hello, i am trying to implement an iverter design with Cadence gpdk45.
my snipping grid is defined 0.005, as shown bellow.
When i ran assura DRC with the rul file of gpdk45.
It says there is off grip shape on layers 14,12,8 although i didnt touch those layers at all.(as shown bellow)
Where did i go wrong?
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Exporting Impedance data from Harmonic Balance after Loadpull analysis
Hi,
I am running load-pull analysis on a circuit for a range of frequencies. I need to use this data in other tools such as matlab. I wondering how to export this data in terms of impedances and plot the variation of optimum impedances with respect to frequency. Thanks.
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pole zero analysis validation using ac sweep
Hello ,i have built a circuit and ran a POLE ZERO simulation on it, after that i took those poles and zeros and made a transfer function in MATLAB as shown bellow.
After that i compared the MATLAB bode plot with AC sweep of the circuit . i get almost the same response however the peak at the AC sweep is much lower then the POLE ZERO transfer function bode plot.
where did i go wrong comparing them?
Thanks
p=[1.9128e-12+5.03292e9i;1.9128e-12-5.03292e9i]
z=[0+0i;-1.58e-21+0i]
k=1
[num,den]=zp2tf(z,p,k)
sys=tf(num,den)
bode(sys)
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captab simulation problem
Hello ,i am trying to imagine the flow of charge in this 1Ghz Flipflop shown bellow ,i have ran both DC and transient captab simulation as shown bellow.
how ever it says that is an syntaxt error but there almost no syntax in this type of simulation (LOG attached).
where did i go wrong?
Thanks
community.cadence.com/.../1200.log.txt
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extraction parameters not recognised in hirarchy simulation
Hello,i have tried to simulate the extraction model of the layout inverter,
i have build a hirarchy and defined the inverter to be the av_extracted file as shown bellow.
However the transient simulation of the test bench doesnt recognise the exctracted capacitors.
The full log txt is attached.
where did i go wrong?
Thanks
community.cadence.com/.../0654.log.txt
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PMOS netlist model Virtuoso syntax
Hello , i have a netlist model for LTSPICE which i want to implement for building an oscilator using spice text i have trying to import the model shown bellow.
however when i do the check and save on spice text editor it marks red the .model line as if its not fitting the standart of some sort, maybe the PCHAN parameter which is level 18 parameter.
where did i go wrong importing this model?
what kinD of cadence virtuoso spice syntax could fit this model if there is a mismatch?
Thanks
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.SUBCKT SMS2001-C d g s
M1 d g s s XSMS2001-C
Rg g s 1G
Db d s dbody
.model XSMS2001-C VDMOS(KP=4.5359 RS=0.0253 RD=0.1143 RG=60.83 VTO=-0.73
+LAMBDA=0.001 CGDMAX=165p CGDMIN=23p CGS=166p TT=720n a=0.77
+m=0.1 Vj=0.67 Cjo=10.0pF PCHAN)
.model dbody d ron=0.1 vrev= 20 vfwd=2
.ends
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Beff parameter and saturation current
Hello i have created 25uA current threw the nmos and pmos at gpdk45nm technology for the purpose of creating an opamp.
For NMOS in gate drain connection(saturation): W=120n L=1.2u
After simulating i got the desired result of 24.9uA current.
beff_nmos=22.7492u (mobility*Cox)
Vth_nmos=320.23m (threshold)
However when i tried to put it in the saturation current formula shown bellow it gives me a result 5 times lower then simulated.
Where did i go wrong interpreting the Model parameter table shown bellow?maybe i should take other parameter instead of Beff to get the fomula match the simulation?
Thanks
I_nmos=C_ox*mobility*0.5*(W/L)*(Vgs-Vt)^2=beff*0.5*(W/L)*(1.8-0.320)^2=22.74*10^-6*0.5((240*10^-9)/(1.2*10^-6))(1.8-0.320)^2=4.9809696 × 10^-6
NMOS:
Vth_nmos=320.23m (threshold)
PMOS parameters
Vt=-0.315
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ENVLP Anaylsis Questions
I've few question regarding ENVLP analysis and wireless simulations within it.
1) Where can I find the actual values of important parameters after the analysis is finished..It seems that part of them are in the netlist file and part of them are in the Spectre log, but some of them are missing...for example - modulationbw, fmspeedup... etc
2) In rflib\lte...is there an option to run Category M1 uplink signals? I saw legacy LTE and NbioT only. Are there any future releases that will expand the LTE signals?
3) The Post processing of wireless spectrum (including plots) takes a lot of time and sometimes the spectrum is computed incorrect (for example, in narrow-band signals). Is there an option to export the envelope data (time domain), and analyse in Matlab for example?
BR
Yaniv
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high frequency D flip flop for phase detector
Hello, i have succeeded to implement a phase detector using modification of xor logic circuit. how ever the more popular implementation is using D FLIP FLOP shown bellow.
I have read many articles explaining the principle and i understand it well, but the simulation always goes bad.
is there some example in the cadence website of D flip flops full simulation? not necessary 5Ghz ,some thing modest i could learn from?
Thank
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icc.rules in cadence 6.1.7
Hi,
I am using virtuoso 617 to do the auto-route by chip assembly router. However, there are some drc errors. I found out online that designer can import icc.rules file to define minimum width and spacing at old version like viruoso 5141. However, I can locate a place where I can import icc.rules file at virtuoso 6.1.7. Can anybody help me or this version has automatically applied icc.rules?
Thanks
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gpdk45 Gate source switch charge injection
Hello, I am trying to simulate a physical phenomena of charge injection from gate to source, as shown in the schematics bellow.
the principal says that when we switch voltage from VDD to 0 on the gate, although the charging has to stop there is still the curent flow from gate to sourse from the overlap parasitic capacitance.
I=C*dv/dt when voltage changes there is a current flow threw the capacitor.However when i tried to simulate this effect in cadence, i got a very idial behavior.
I trying to change the Width of the NMOS ,rise time fall time, it presents me an idial behavior.
Is there something i can do to see this effect in cadence virtuoso?
Thanks
FYI This is yefj , i had problem with my user and i was told by the cadence support to re-register :-) i will change my nick as soon as possible.
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