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Calculating Phase Noise from PSS-shooting simulation
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Modelling noise in a DC current source
Hi,
I would like to know how to model noise in a DC current source. I want to model reference current RMS output noise which is taken from the practical current source datasheet. I would like to know how can I model these noise parameters in cadence current source to see the effects of DC noise in my cadence simulation. Thanks!
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Injection lock vco
Hi all,
Is there any guide that helps me simulate an injection locked vco ?
All I know for now is: run a transient simulation and let my oscillator reach the steady state and then I use a switch to connect the Injection voltage using a varactor and wait for it to lock to finj.
How can I obverse the final fundamental tone using pss ? Can I observe phase noise using pnoise simulation ?
Do pss and pnoise work with switch component ?
This is what I am planning to do. Using a switch to connect the injection signal to VCO using two varactors.
Thank you. I appreciate your time and effort.
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port calibration in EMX
Dear RF experts,
I have a few questions about EMX:
- In the EMX documents, port calibration is not mentioned anywhere. Could you tell if EMX is capable of doing this, or the calibration is already embedded inside EMX?
- When EM simulating the interconnects to transistors up to ~300GHz, we need to strip off the transistors and place 3-4 closely placed ports (either edge or internal ports) for the transistor terminals. Could EMX calibrate the ports as a group (remove the parasitics among the ports)? Is it better to use edge ports or internal ports in this case?
Thank you a lot and regards,
Anh
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identification of diode and monolithic amplifier
hi, I need to identify the components in the circuit. Its noise source, old and from china. In left corner it must be zener diode, next to it monolithic amplifiers. If you have experience with these, please let me know.thx
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Why don't PAE vs PT (Total Power) measurements agree?
Hello,
I'm tuning an NXP LDMOS FET model in Microwave Office. When my Vds current is about 20A at 12V, my output power on port 2 measured by the "PT" Total Power measurement shows ~100W (which is our optimization target).
Here is the part I don't understand: Why does PAE show about 75%? Shouldn't 100W/240W have a PAE of ~41%?
Port 1 (Pin) is 17dBm, so 0.050 Watts, a negligible amount.
(Pout-Pin)/Pdc == (100-0.050)/240W == 0.416.
What am I missing here?
Thanks for your help!
-Eric
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Transient Assisted Harmonic Balance
I am designing a 3-port circulator circuit that mixes an RF input with a local oscillator. The oscillator is custom design and not a ideal source. I have tried hb simulation with the oscillator defined and then ran hbsp with no success. The oscillator is not converging with I run the hb. However, when i run a transient analysis the oscillator is functioning correctly.
How can I run a Harmonic balance simulation with the oscillator and view the s-parameters of the circulator at all three ports.
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Large signal sp analysis in virtuoso
How is it possible to perform a large signal analysis for a varactor? I have used lssp from hb analysis but it isn't give results for a varactor.
Thanks!
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Usage of PN() after transient noise simulation
In this document: Virtuoso Spectre Transient Noise Analysis
The PN() function is used to calculate the phase noise after transient simulation with this equation: (p.55)
What's the reason for the last term: dB20(twoPi*f0_pss), i.e. dividing the power by 2*pi*Fc ?
I'm confused how the PN() function implements the calculation of phase noise as defined in the same document: (p.53)
Does it automatically normalized the jitter power to signal power as the equation in this another document: Jee Measurement using PSS/Pnoise and Transient Noise Analysis? (p.33)
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Strange transient behavior of an LC-oscillator
Hi, I’m trying to do transient simulation for my LC-oscillator, intended for ~260GHz. I first em-simulated the inductor and interconnects using EMX to extract an S-parameter data file and then embeded the file into my transient sim testbench using nport. The emx simulation was done from DC-900GHz to cover the 3rd harmonic (see the 1st image below). The nport settings are in the 2nd image. The settings for transient sim: conservative accuracy, transient noise 100-300GHz, traponly, timestep ensuring > 100 timepoints/cycle. The transient simulation results are in image 3. The frequency and amplitude are as predicted (255GHz, 1.5Vpp) until about 400ps, from which the frequency jumps to ~732GHz and the amplitude increases with time to very large value ~9Vpp. The fmax of my transistors is about 450GHz so the 732GHz frequency is impossible. The simulation's output log is shown on image 4 and 5, with causality check and minimal time-step warnings. I have then tried two things:
- Suspecting that the causality check could make the S-param data to become non-passive, I changed the causality correction to "No" in the nport setting. The simulation results however are quite the same, with a sudden jump of the frequency. The oscillation amplitude increases to ~20V before the simulation terminates itself with a warning "device is melting". The results are also the same when the nport's causality correction was changed to "fmax".
- Changed the integration method to euler and gear2. The 250GHz oscillation part then disappeared but the 732GHz part stayed almost the same as before.
I'm pretty sure the strange frequency jump is a simulation artifact but have little clue where it comes from and how to fix it. Could you please give a hint here?
Many thanks and regards,
Anh
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Interstage matching in Cadence Virtuoso
Hello,
I am trying to create a multistage amplifier operating around 200 GHz in Cadence Virtuoso. Could someone tell me how I can measure the impedances at intermediate nodes? I need this so that I can do conjugate matching between stages.
In the past, I have designed amplifiers using ADS. I used 'SP probe' between the stages to measure impedances. Is there something similar in Cadence Virtuoso?
I read something about 'sprobe' in cadence forums. I think I need to use that block. But unfortunately, I could not find it in my analogLib. Has it been added recently? Or am I missing something? (I'm using IC617)
Thanks.
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multiple S-parameter Simulation touchstone save
Hi
I want to do an S-parameter simulation and sweep a design variable in ADE XL setup and save each S-parameter results in a separated touchstone file
But when I give an address in Output Parameter 'file' field, it just saves last simulation result in sweep
I don't know how can save all results
Thanks
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bbspice fitting process taking too much time
Hi,
I have an S parameter file generated by EMX for my oscillator. It has 56 ports and was simulated from DC-900GHz with a 1GHz step. When I used bbspice as the interpolation method for the nport, the rational fitting takes almost 1 day and still has not finished. Could you suggest some techniques I could use to reduce the fitting time? Here I have kept the nport compression as default. I'm curious since Tawna mentioned in an earlier thread that she used to simulate an n-port with 405 ports (https://community.cadence.com/cadence_technology_forums/f/rf-design/37979/how-to-compare-what-spectre-interprets-from-the-raw-s-parameter-file/1352837#1352837).
I'm using Spectre Version 16.1.0.510.isr10 64bit -- 13 Oct 2017, Virtuoso IC6.1.7-64b.500.15, EMX 5.12, interface date 15/7/2020.
I include here the settings for my nport, and the screenshot from transient simulation showing the iterations of the fitting process.
Many thanks and regards,
Anh
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Unable to run cds_srr commands in matlab
Here is my simple matlab script:
import cadence.srrdata.*
import cadence.Query.*
import cadence.utils.*
resdir = '/nfs/sc/disks/xyz_dts_tb/maestro/results/maestro/Interactive.47/1/xyz_noise/psf';
datasets = cds_srr(resdir);
Here is the error:
--------------------------------------------------------------------------------
Matlab default startup completed.
Running Intel workaround to prevent >200MB disk usage in your home directory.
Done.
--------------------------------------------------------------------------------
>> spectre_matlab1
Invalid MEX-file '/p/hdk/cad/mmsim/19.1.0.561/tools/spectre/matlab/64bit/cds_innersrr.mexa64': /nfs/site/disks/hdk_cad_3/cad/matlab/R2016a/bin/glnxa64/../../sys/os/glnxa64/libstdc++.so.6: version `GLIBCXX_3.4.20' not found (required by
/p/hdk/cad/mmsim/19.1.0.561/tools/spectre/matlab/64bit/../../../lib/64bit/libsrr.so)
Error in cds_srr (line 16)
sig = cds_innersrr(dirname);
Error in spectre_matlab1 (line 7)
datasets = cds_srr(resdir);
Matlab Env:
MATLAB=/nfs/site/disks/hdk_cad_3/cad/matlab/R2016a
BASEMATLABPATH=/p/hdk/cad/mmsim/19.1.0.561/tools/spectre/matlab/64bit:/p/hdk/cad/mmsim/19.1.0.561/tools/spectre/matlab/:/nfs/sc/disks/axx_0419/sriharsh/1276_vmac/vmac_dts_21ww03p5a/matlab:/p/hdk/cad/analog_collateral/18.14.2/libraries/matlab/
OSG_LD_LIBRARY_PATH=/nfs/site/disks/hdk_cad_3/cad/matlab/R2016a/sys/openscenegraph/lib/glnxa64
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VCO verilog-A model not running pss
Dear all,
I am running a pss of a simple VCO verilog-A model, but there is an error found and pss is failed:
Warning from spectre.
WARNING (SPECTRE-16707): Only tran supports psfxl format, result of other analyses will be in psfbin format.
Error found by spectre during periodic steady state analysis `pss'.
ERROR (SPCRTRF-15177): HB analysis doesn't support behavioral module components with hidden states found in component 'vco_8G_pss'. Skipped.
Error message from ahdl:
/home/SSS/vco_8G_pss/veriloga/veriloga.va, at line 33: idtmod not support in hb analysis.
/home/SSS/vco_8G_pss/veriloga/veriloga.va, at line 34: idtmod not support in hb analysis.
Rewrite the module and rerun.
Analysis `pss' was terminated prematurely due to an error.
modelParameter: writing model parameter values to rawfile.
And here is the code I used in VCO verilog-A model:
`include "discipline.h"
`include "constants.h"
`include "constants.vams"
`include "disciplines.vams"
(* instrument_module *)
module vco_8G_pss(vin, voutP, voutN);
input vin; voltage vin; // input terminal
output voutP, voutN; voltage voutP, voutN; // output terminal
parameter real vmin=0; // input voltage that corresponds to minimum output frequency
parameter real vmax=2 from (vmin:inf); // input voltage that corresponds to maximum output frequency
parameter real vc=1/2*(vmax+vmin) from (vmin:inf); // maximum output frequency
parameter real fmin=7.372e9 from (0:inf); // minimum output frequency
parameter real fmax=8.628e9 from (fmin:inf); // maximum output frequency
parameter real fc=1/2*(fmax+fmin) from (fmin:inf); // maximum output frequency
parameter real va=1; // amplitude
parameter real kvco=100M;
real freq, phaseP, phaseN;
integer n;
analog begin
// compute the freq from the input voltage
// freq = (V(vin)-vc)*(fmax - fmin) / (vmax - vmin) + fc;
freq = kvco*(V(vin)-vc) + fc;
// bound the frequency (this is optional)
if (freq > fmax) freq = fmax;
if (freq < fmin) freq = fmin;
// phase is the integral of the freq modulo 2 pi
phaseP = 2*`M_PI*idtmod(freq, 0.0, 1.0, -0.5);
phaseN = `M_PI+2*`M_PI*idtmod(freq, 0.0, 1.0, -0.5);
V(voutP) <+ va*(1+sin(phaseP));
V(voutN) <+ va*(1+sin(phaseN));
// bound the time step to assure no cycles are skipped
$bound_step(0.2/freq);
end
endmodule
Is there any approach to run pss in VCO verilog-A model?
Looking forward any responses.
Thanks all.
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Internally Connected Pins on Cell Layouts are Not Working
We created a cell footprint for a shield inductor for my HF radio project. The shield has multiple pins, so we assigned all of those pins as cell port 3. When we connect to one of the shield cell ports, it should connect to the other side, but ratlines clearly show that it does not when connecting both shield pins as intended. I tried playing with cell port groups and put both cell port pins in the same group (Group 3) but that did not help. The group type is set to strong and the help page for cell ports says that strong should allow conductivity between pins, but it does not.
You can see from the picture, that the top pin and the bottom pin should be connected, but they already are because they are both port 3. This is a sub-circuit and the light colored iNet in the bottom left corner of the picture is in the sub-circuit, but the dark the dark purple is outside of the sub-circuit. This inductor component has a FET component in the middle of the inductor that switches the inductor. It is a sub-circut because we need to re-use it 18 times in the layout. Here is my first video explaining what we are trying to do:
Thank you for your help!!1
-Zeke
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ISF Simulation using Transient Analysis by injecting Impulse
Hi ,
I am trying to get the Impulse Sensitivity function for Ring Oscillator so I am trying to follow the below steps:
i) First I am simulating the oscillator unperturbed and get the unperturbed waveform.
ii) Then I am injecting small current impulses at time instant t1, between nodes of interest with an area del q. So as a result I am getting oscillator output shifted in time domain depending upon at what time instant I am injecting the impulse current.
iii)Then I repeat the step 2 for N number of times in one period to get different N waveforms (link below)
So I want to know is there a way in cadence in which I can find del t i.e find time shift occurred due to current injection for N different outputs . and plot the ISF in the same window using the formula (2*pi/T0)*(del q/Qmax).
Thanks
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Phase response of injection locked ring oscillator
Hi,
I have designed a first harmonic injection locked quadrature oscillator (First harmonic means - input and output are at the same frequency. It is not a divider). It accepts a differential input and produces quadrature outputs at the same frequency. I need to measure quadrature accuracy of the output and injection locking range of oscillator. Can any one help me finding out locking range and quadrature accuracy?
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Phase noise and jitter simulation
I have a clocking circuit containing 2 stages, a buffer followed by a divider. I used pss with shooting method +pnoise to simultate the Rj. Assume that the clock frequency is fin at the input of the buffer and fin/2 at the output of the divider. (fin is between 10~20GHz). The beat frequency is set to be fin/2 so that pss can converge.
Rj at the 1st stage output is then calculated in two ways:
1. Use Jee in the direct plot form. The integration range is 1M~fin/2
2. Use Edge phase Noise in the same form to plot phase noise, and integrate the noise 1M~fin/2, convert it to Rj with respect to 2*pi*fin
Now the problem is that the Jee gives exactly twice the number of method 2. Does this mean that Jee rely on beat frequency to calculate the phase jitter instead of the real frequency?
When there are circuits operating in different frequencies, should users manually compensate the difference between beat frequency and real signal frequency if Jee is used to calculate Rj?
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Harmonic Balance Convergence Issue
Hi
I'm running hb and hbnoise to plot the phase noise of a clock divider that divides a 4.5-GHz clock by 10, but the simulation doesn't converge.
I configured the oversample factor to 8 (and tried 16) as the input is a square wave, number of harmonics = 5 (read in the user guide that as the oversample factor increases, number of harmonics could be small and give correct results). The circuit runs successfully in transient analysis and the waveform is generated after less than 1ns yet I configured the hb to run tran first for 5ns and save initial results. I configured the fundamental freq. as 4.5G and Freqdivide ratio=10, and accuracy is moderate.
I read somewhere that fundamental freq should be the divided one (4.5G/10) as it's the least freq in the circuit but I think in this version (cds 6.1.7) I should put the input freq (4.5G) as the sim already asks for the division ratio.
I should also note that sometimes a warning appears in hb log says the transistor leaves the linearized region (meaning the MOS PN junctions became forward), yet when transient analysis is chosen, the warning doesn't appear and the results are correct! Meaning it's a measurement error.
Thanks in advance
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